1. Field of the Invention
The present invention relates to a method for analyzing semiconductor process parameters, and more particularly, to a method for analyzing final test parameters.
2. Description of the Prior Art
In the arena of semiconductor manufacturing, many processes, such as photolithography processes, etching processes, ion implantation processes, etc., are required to complete the fabrication of a semiconductor product. A large amount of equipment and complicated procedures are required in a semiconductor manufacturing process. Therefore, engineers in the field spend a great deal of time ensuring the proper operation of equipment, sustaining or improving production yield rates, detecting and verifying problems, and periodically maintaining facilities for production and the like so as to ensure that overall operations are in good order, and to ensure the production of satisfactory products.
In order to identify semiconductor processing problems, data such as process parameter data, in-line quality control (in-line QC) data, defect inspection data, sample test data, wafer test data, and final test data, are analyzed. The final test data contains testing values acquired by performing testing of semiconductor devices after dicing and packaging procedures.
Please refer to FIG. 1. FIG. 1 is a flow chart of a prior art method for analyzing final test parameters. As shown in FIG. 1, step 101 is first executed by an engineer to perform various final test items upon each semiconductor device after the packaging process. For example, the testing of certain electrical characteristics is performed on the pins of the semiconductor devices.
Step 102 is then executed. In step 102, the results acquired from various final test items performed upon each semiconductor device is analyzed by an engineer to detect product having abnormal final test results.
In step 103, the possibly faulty process step or the possibly faulty testing step is determined by way of personal experience acquired by an engineer, and is based upon the final test results of the abnormal products selected from step 102. A possibly faulty process step may be, for example, a packaging process, and the possibly faulty testing step, for example, may be an in-line quality control step, a sample test, etc.
Finally, step 104 is executed. In step 104, the engineer identifies the malfunctioning equipment by checking the equipment utilized in the process step determined in step 103, or reset various preset values of the testing step determined in step 103. For example, the engineer may first determine that one of the pins in the semiconductor device is out of order, search for the process step in which the packaging process is performed, and find out which equipment is malfunctioning, such as the wire bonding equipment, the molding equipment, etc. In addition, if the engineer determines that the problem of the semiconductor device is correlated to a previous manufacturing processes, then it can be assumed that an in-line testing step, executed previously, has also probably gone wrong, to cause the problematic products are not able to be checked out. Under such circumstances, the engineer will have to revise various predefined specs of the in-line testing step to ensure that the problem is not repeated. However, since the analysis results (step 103) and the revised numerical values (step 104) are determined according to an engineer's personal experience, the accuracy and confidence level of the final analysis results are open to question. Furthermore, human resources in semiconductor manufacturing plants change frequently. It is not easy to transfer an engineer's personal experience. The capacity of each engineer is a limited resource, meaning that the engineer is unable to look after the operational status of all the equipment in the plant. When the testing results from semiconductor products indicate abnormalities, it is often difficult for engineers, lacking in experience, to rapidly and correctly determine which process point is responsible for the problem. As a result, a lot of time is wasted to undertake related research, and even worse, incorrect decisions are made. This will not only reduce process efficiency, but also increases costs. Furthermore, the in-line production status cannot be improved in time to increase the yield rate.
It is therefore very important to provide an analytical-method to rapidly and correctly determine which point in a semiconductor manufacturing process has caused a problem to occur, and to correct the predefined specs when the final test data of the semiconductor products indicates abnormalities.